1. Field of the Invention
The disclosed technology relates to on-chip testing using time-to-digital conversion, and more particularly, although not exclusively, to testing of through-silicon-vias mounted on three-dimensional stacked integrated circuits.
2. Description of the Related Technology
The semiconductor industry is moving towards utilizing three-dimensional stacked ICs (3D-SICs) based on through-silicon-vias (TSVs). TSVs are conducting elements which extend out of the back-side of a thinned-down die or wafer and which enable a vertical interconnection to be made to another die. TSVs are high-density, low-capacity interconnects compared to traditional wire-bonds, and hence allow for many more interconnections between stacked dies or wafers, while operating at higher speeds and consuming less power. TSV-based 3D technologies enable the creation of a new generation of ‘super chips’ by opening up new architectural opportunities. Combined with their smaller form factor and lower overall manufacturing cost, 3D-SICs have many compelling benefits, and hence their technology is quickly gaining ground.
Like all micro-electronics, the manufacturing process of TSV-based die or wafer stacks is sensitive to defects, and hence 3D-SICs need to undergo electrical testing to filter out the defective dies or wafers to ensure product quality. Testing might take place before and/or after stacking, respectively known as pre-bond die tests and post-bond stack tests. The tests ideally cover not only intra-die defects, but also defects in TSV-based interconnects. A TSV-based interconnect consists of the TSV itself and the bond between the TSV tip in one die and the TSV landing pad in another die. In alternative implementations, the bond is made between two micro-bumps.
Conventionally, interconnects are tested by applying an electrical signal at one end of each interconnect and electrically observing the applied signal at the other end of the same interconnect. The correct and in-time arrival of the signal indicates the integrity of the particular interconnect being tested. However, this method of testing requires full electrical access to both sides of the interconnect being tested.
In pre-bond die testing on thick (not-yet-thinned) wafers, the TSVs are accessible from at most one side, as the other side is still deeply buried inside the (not-yet-thinned) wafer. A potential solution to this problem is to test the TSV on a thinned wafer where the TSVs are exposed on both sides and are no longer buried inside the substrate of the wafer. However, thinned wafers are very thin, typically having a thickness of between 25 μm and 50 μm, and hence are mechanically fragile. They tend to exist only in mounted form, mounted with some sort of glue on top of a carrier, for example, silicon or glass. This means that the front-side of the wafer is no longer available for probe access in the testing process. Probing on a thinned wafer is therefore, by definition, back-side probing only. Potentially, this could allow for dual-side access to the TSV as the TSV under test could be contacted at its exposed tip while the other side is accessed from the back-side via another TSV.
However, there many uncertainties involved with back-side probing of thinned wafers on a temporary carrier, including the risk of cracking and/or breaking of the thinned wafer, temporary and/or permanent damage to the circuitry and TSVs, etc. In addition, probing on exposed TSV tips or TSV-mounted micro-bumps is far from easy with probe technology currently in use as TSVs are too small, too fragile, and too numerous.
Two alternative approaches for single-side access for testing are known from articles entitled “Through Silicon Via (TSV) Defect/Pinhole Self Test Circuit for 3D-IC” by Menglin Tsai, Amy Klooz, Alexander Leonard, Jennie Appel, Paul Franzon (North Carolina State University), IEEE International 3D System Integration Conference (3D-IC'09), San Francisco, Calif., September 2009 (http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5306569&isnumber=5306519) (Menglin et al.); and entitled “On-Chip TSV Testing for 3D IC before Bonding Using Sense Amplification” by Po-Yuan Chen, Cheng-Wen Wu, Ding-Ming Kwai (National Tsing Hua University, ITRI), IEEE Asian Test Symposium (ATS'09), Taichung, Taiwan, November 2009, pages 454 to 459, (http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5359278& isnumber=5359187) (Chen et al.).
In the article by Menglin et al., a method is described which uses a leakage-current test for detecting TSV-to-substrate shorts due to pinholes in the TSV oxide walls. Analogue test circuitry is provided per TSV, and hence might prove costly in case of having to carry out testing of many TSVs. Moreover, the method requires a very accurate clock distribution to the test circuitry, and does not cover the testing of TSV open circuit defects. In addition, the article does not appear to take into account the fact that TSVs are not manufactured for test purposes only, but need to carry functional signals in their normal operational mode.
In the article by Chen et al., a method is described which tests for both TSV open and short circuit defects by means of writing a digital value, either 0 or 1, to a TSV and determining its discharge time by means of a sense amplifier circuit as found in dynamic random access memory (DRAM) devices. The test infrastructure is per TSV and hence quite costly in the case of having to test many TSVs.